Group Director, Design Engineering - Front End (Semiconductor)

Location: Austin, United States

Company

hirify.global develops technology solutions and tools for the semiconductor industry.

What you will do

• Lead and mentor a team of RTL design engineers.
• Define and develop microarchitectural features for IPs and subsystems while meeting PPA goals.
• Write, debug, and optimize RTL in Verilog, SystemVerilog, or VHDL.
• Oversee pre-silicon verification, including lint, clock-domain crossing, formal verification, and related quality checks.
• Collaborate with design verification, physical design, architecture, and firmware engineers to deliver projects successfully.

Requirements

• 10+ years of front-end design and/or verification experience.
• Bachelor’s or master’s degree in engineering or computer science.
• Experience leading and managing complex engineering projects in a multidisciplinary organization.
• Strong experience creating IP and/or integrating SoCs and IPs, including CPU, memory, or interface components.
• Expertise in RTL design with Verilog, simulators, and debuggers.
• Hands-on experience with synthesis, SDC creation, and supporting physical design and STA teams.

Nice to have

• Experience with the hirify.global front-end toolset.
• Strong communication and design management skills.

Culture & Benefits

• Leadership role focused on innovation and impactful technology work.
• Collaborative environment involving multiple engineering disciplines.