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Photolithography Process Engineer (MEMS)

109 700 - 175 500$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Photolithography Process Engineer (MEMS): Developing and sustaining unit processes for high-volume Si MEMS production with an accent on photolithography tool ownership, process characterization, and statistical validation. Focus on optimizing ASML i-line steppers, managing CD/overlay SPC, and driving yield improvements in a dynamic manufacturing environment.

Location: Must be based in Fort Collins, Colorado, USA

Salary: $109,700 - $175,500

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

  • Develop and characterize robust photolithography solutions for R&D and high-volume manufacturing needs.
  • Manage photo processes on ASML i-line steppers and high-topography exposure systems.
  • Monitor CD and overlay SPC charts and perform layer defect monitoring.
  • Collaborate with Equipment Engineering and R&D to conceptualize and implement process improvements.
  • Conduct experimental design and data analysis to resolve yield and defect issues.
  • Organize and manage long-term improvement projects to meet organizational goals.

Requirements

  • Legal authorization to work in the U.S. is required.
  • BS in EE, ME, ChE, Materials Science, Physics, or Chemistry with 8+ years of experience (or MS with 6+ years, or PhD with 3+ years).
  • Deep expertise in photolithography, specifically with ASML equipment (PAS5500) and track systems (TEL_ACT8).
  • Strong background in Statistical Process Control (SPC) and data analysis tools like JMP, Minitab, or Spotfire.
  • Understanding of silicon-based MEMS device applications and interdependencies with other unit processes.
  • Proven ability to work in a dynamic, high-volume manufacturing environment.

Nice to have

  • Experience with Wafer-Level Packaging (WLP) or through silicon vias (TSVs).
  • Knowledge of thick resist processing such as polyimides or chem amp resists.
  • Practical experience in Fault Detection & Classification (FDC) systems, Copy Exactly (CE!) methodology, or Lean manufacturing.

Culture & Benefits

  • Competitive base salary with discretionary annual bonus eligibility.
  • Equity award opportunities connecting success to company growth.
  • Equal opportunity employer committed to a diverse and inclusive workplace.
  • Opportunity to work on cutting-edge MEMS technologies in a high-volume production environment.

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