Назад
Company hidden
обновлено 5 дней назад

Physical Design Engineer (Semiconductor)

152 700 - 203 600RON
Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
Romania
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Physical Design Engineer (Semiconductor): Creating physical designs for next-generation processor chips by running RTL through synthesis and place-and-route tools, with an accent on advanced CMOS technologies, timing analysis, and power-grid verification. Focus on reviewing sign-off checks, analyzing complex chip performance, and optimizing robust physical design methodologies.

Location: Onsite in Bucharest, Romania

Expected base pay: 152,700–203,600 RON per annum

Company

hirify.global develops semiconductor solutions and data infrastructure technologies for enterprise, cloud, AI, carrier, server, 5G/6G, and networking applications.

What you will do

  • Develop the physical design of complex processor and ASIC chips using leading-edge CMOS process technology.
  • Run RTL code through synthesis and place-and-route tools to create chip physical views.
  • Analyze performance through timing analysis and verify power-grid integrity with EMIR analysis.
  • Review sign-off runs for errors and optimize successful design runs.
  • Contribute to physical design methodology for efficient and robust design processes.
  • Collaborate with a global team on high-performance chip designs for server, 5G/6G, and networking applications.

Requirements

  • Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
  • Good written and verbal English.
  • Willingness to learn through hands-on work, guidance, and mentorship.
  • Willingness to volunteer for new learning opportunities.
  • Applicants may be subject to an export license review before accessing export-controlled technology or software.

Nice to have

  • Physical design experience focused on block-level place and route for advanced CMOS process nodes.
  • Experience with industry-standard EDA tools for RTL synthesis, physical design, static timing analysis, or physical verification.

Culture & Benefits

  • Competitive compensation and benefits.
  • Collaborative, transparent, and inclusive work environment.
  • Tools and resources for professional growth and development.
  • Work on long-term semiconductor and data infrastructure innovation.

Hiring process

  • Interviews evaluate individual experience, thought process, and communication skills in real time.
  • AI tools, transcription applications, automated answer generators, and note-taking bots are not permitted during interviews.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →