Physical Design Engineer (Semiconductor)

TL;DR

Physical Design Engineer (Semiconductor): Developing physical design and methodology for next-generation high-performance processor chips with an accent on RTL synthesis, place and route (PnR), and sign-off verification. Focus on optimizing complex CMOS designs for server, 5G/6G, and networking applications while ensuring robust performance and power grid integrity.

Location: Onsite in Bucharest, Romania

Salary: 152,700–203,600 RON per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential data infrastructure technology for cloud, AI, and enterprise architectures.

What you will do

• Collaborate with a global team on physical design and methodology for complex processor chips.
• Execute RTL synthesis and place and route (PnR) to create physical chip views.
• Perform static timing analysis and EMIR analysis to verify power grid integrity.
• Review completed design runs for errors and implement optimizations.
• Ensure database readiness for subsequent design stages.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Must be eligible to access export-controlled information under U.S. law.
• English proficiency required for verbal and written communication.
• Experience with block-level PNR for advanced CMOS nodes is a plus.
• Familiarity with industry-standard EDA tools for synthesis, timing analysis, or physical verification is a plus.

Culture & Benefits

• Work within a collaborative, transparent, and inclusive global environment.
• Access to mentorship and structured learning opportunities.
• Opportunity to contribute to high-impact, enduring semiconductor innovation.
• Competitive compensation package.

Hiring process

• Interviews will evaluate individual experience and communication skills in real time.
• AI tools (transcription, ChatGPT, etc.) are strictly prohibited during interviews and will result in disqualification.