Senior RTL Engineer

TL;DR

Senior RTL Engineer: Designing and developing microarchitecture and complex logic systems for SoC applications with an accent on RTL coding, Lint checks, and CDC testing. Focus on collaborating with physical design and synthesis teams to meet performance, power, and area goals while supporting design flows and tools.

Location: Based in Romania (Brasov, Bucharest, Cluj-Napoca, Iasi, or Timisoara)

Company

hirify.global is a global business and technology transformation partner with over 340,000 team members across 50 countries, specializing in digital and sustainable engineering solutions.

What you will do

• Own feasibility studies for system architecture, requirements, and external interfaces
• Develop microarchitecture and logic design in collaboration with functional leads
• Perform RTL coding, Lint checks, CDC tests, and timing constraint creation
• Work closely with synthesis, STA, PD, and DFT teams to optimize performance, power, and area
• Develop and maintain internal design flows and tools to support R&D activities

Requirements

• Minimum 8 years of professional experience in VLSI design
• BSc or MSc degree in Electrical or Computer Engineering
• Strong proficiency in Verilog, SystemVerilog, or VHDL
• Proven experience in SoC design and advanced design practices including Lint and CDC
• Knowledge of backend synthesis and STA tools
• Experience with scripting and automation using Perl, C, or Python

Nice to have

• Familiarity with ARM, RISC-V, or x86 instruction sets
• Understanding of verification methodologies

Culture & Benefits

• Access to extensive professional development including certifications and training platforms
• Comprehensive medical services and dental/vision support coverage
• Employee Assistance Program for financial, legal, and emotional support
• Flexible working hours to support work-life balance
• Participation in the Employee Share Option Plan