Physical Verification Engineer (Semiconductor)

TL;DR

Physical Verification Engineer (Semiconductor): Providing specialized technical support for layout verification and parasitic extraction for aerospace and defense applications with an accent on advanced CMOS processes (22nm and below). Focus on resolving complex verification challenges, driving methodology improvements, and ensuring successful customer tape-outs.

Location: Must be based in the US (Phoenix, AZ; Santa Clara, CA; or Hillsboro, OR) with a hybrid work model.

Salary: $128,880–$245,160 USD

Company

hirify.global is a global leader in semiconductor manufacturing and foundry services, delivering cutting-edge silicon process and packaging technology for the AI era.

What you will do

• Provide technical support to foundry customers on layout verification and parasitic extraction.
• Collaborate with internal teams, IP providers, and EDA vendors to resolve complex design rule and extraction issues.
• Create application notes, documentation, and technical training for customers and internal teams.
• Lead the optimization of physical verification flows for advanced CMOS processes.
• Develop best practice guidelines for DRC, LVS, ERC, and PERC implementations.
• Drive methodology improvements to streamline customer design workflows and enhance productivity.

Requirements

• US Citizenship required due to the nature of the work.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a STEM field.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience in layout verification and parasitic extraction EDA tools.
• 3+ years of experience in scripting languages (Python, Perl, Tcl, or shell).

Nice to have

• Active US Government Security Clearance (Secret level or higher).
• Post-graduate degree in a STEM field.
• Hands-on experience with LVS, DRC, ERC, or PERC.
• Experience with parasitic extraction tools like StarRC, Quantus, or xACT.
• Experience with layout editing tools such as ICV, Calibre, or Pegasus.
• Customer-facing experience and technical leadership skills.

Culture & Benefits

• Competitive compensation package including pay, stock bonuses, and comprehensive benefits.
• Access to industry-leading semiconductor verification technologies and tool suites.
• Professional development opportunities in advanced foundry methodologies.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Direct impact on national security through advanced semiconductor solutions.