Full-Chip Physical Design Verification Engineer (AI)

TL;DR

Full-Chip Physical Design Verification Engineer (AI): Driving full-chip signoff and ensuring manufacturable, high-quality silicon across advanced technology nodes with an accent on physical verification closure (DRC, LVS, ERC) and cross-functional collaboration. Focus on debugging complex verification flows, implementing ESD planning, and ensuring successful tapeouts for next-generation AI platforms.

Location: Hybrid (based out of Santa Clara, CA or Austin, TX or Fort Collins, CO). Candidate must be eligible to access U.S. export-controlled technology (EAR compliance).

Compensation: $100k - $500k (including base and variable)

Company

hirify.global is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency.

What you will do

• Drive full-chip signoff to ensure manufacturable, high-quality silicon across advanced technology nodes.
• Lead physical verification closure, including DRC, LVS, and ERC.
• Debug complex verification issues using standard industry PV tools.
• Collaborate with RTL, PD, CAD, and packaging teams to achieve successful tapeouts.
• Mentor and provide technical leadership to build efficient and scalable PV methodologies.

Requirements

• BS/MS in Electrical/Electronics Engineering or a related field.
• 7–14 years of hands-on CPU/IP/SoC physical verification experience.
• Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM using tools like Calibre, ICV, Pegasus, FC, or Innovus.
• Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM).
• Solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
• Proficiency in Python and TCL for automation and flow optimization.
• Eligibility for U.S. export license ( EAR Country Groups D:1, E1, or E2 restrictions apply).

Culture & Benefits

• Highly competitive compensation package and benefits.
• Environment that values collaboration, curiosity, and solving hard problems.
• Opportunity to work with a diverse team of technologists on a high-performance RISC-V CPU.
• Equal opportunity employer.