Senior Principal Physical Design Engineer

TL;DR

Senior Principal Physical Design Engineer: Leading advanced physical design activities for complex SoC and IP blocks with an accent on performance, power, and area optimization. Focus on driving RTL to GDSII implementation, mentoring engineering teams, and advancing design methodologies for cutting-edge semiconductor products.

Location: Leuven, Belgium

Company

hirify.global is a global leader in secure connectivity solutions for embedded applications.

What you will do

• Lead and execute physical design for large-scale digital designs from RTL to GDSII.
• Optimize design methodologies, flows, and scripts to improve efficiency and quality.
• Perform critical path analysis and implement solutions to meet aggressive power and frequency targets.
• Collaborate with architecture and verification teams to resolve complex technical implementation issues.
• Mentor junior and mid-level engineers to foster technical growth within the team.
• Evaluate and integrate new EDA tools to enhance physical design capabilities.

Requirements

• Bachelor's or Master's degree in Electrical or Electronics Engineering.
• 15+ years of extensive experience in ASIC physical design with a track record of successful tape-outs.
• Deep expertise in industry-standard EDA tools like Cadence Innovus, Synopsys Fusion Compiler, or Ansys RedHawk.
• Proficiency in scripting languages including Tcl, Perl, and Python.
• Strong understanding of static timing analysis, low-power design techniques, and semiconductor physics.
• Demonstrated ability to lead technical initiatives and mentor engineering staff.

Culture & Benefits

• Opportunity to work on cutting-edge semiconductor products at a global industry leader.
• Collaborative environment focused on innovation and technical excellence.
• Professional development through mentorship and exposure to advanced EDA technologies.