Analog Layout Engineer (FinFET)

TL;DR

Analog Layout Engineer (FinFET): Designing and implementing high-quality analog layouts for advanced technology nodes with an accent on DRC/LVS closure and performance optimization. Focus on EM/IR analysis, mitigating parasitic effects, and implementing precision matching techniques.

Location: Romania (Timisoara, Cluj-Napoca, Iasi, Bucharest, Brasov)

Company

Global leader in engineering services providing R&D and digital technology experts across multiple industries.

What you will do

• Develop analog layouts for circuits such as amplifiers, references, bias blocks, and data converters in FinFET nodes.
• Apply best practices for DRC/LVS closure and efficient debugging.
• Perform EM/IR analysis and implement layout changes to meet reliability targets.
• Address parasitic effects through careful routing, shielding, and post-extraction corrections.
• Implement matching techniques including common-centroid, interdigitation, and dummy devices.
• Collaborate with circuit designers to optimize layout for performance and yield.

Requirements

• Solid experience in analog layout design for analog IP.
• Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies.
• Proficiency in industry-standard EDA tools: Cadence Virtuoso, Calibre, and PVS.
• Familiarity with parasitic extraction flows and correlation techniques.
• Understanding of reliability mechanisms such as BTI and HCI.

Culture & Benefits

• Collaborative and inclusive environment with teams across global locations.
• Flexible working hours.
• Access to professional development, training programs, and certifications.
• Medical services, eye glasses coverage, and meal tickets.
• Employee Assistance Program and Employee Share Option Plan.