Analog Layout Manager (Semiconductor)

TL;DR

Analog Layout Manager (Semiconductor): Leading a team of layout designers to develop high-speed SerDes PHY and Analog Mixed-Signal IPs with an accent on layout methodology and risk assessment. Focus on optimizing macro-level layouts, ensuring DRC/LVS compliance, and synchronizing schedules across CAD and circuit design teams.

Location: Toronto, Canada

Salary: 132,200 - 176,200 CAD per annum

Company

hirify.global is a semiconductor solutions provider creating essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Lead a team of full-time and contract senior layout designers.
• Assess schedules, floor plans, and risks for analog macros.
• Perform hands-on macro-level layout work.
• Manage and track layout schedules, including hiring additional designers as needed.
• Coordinate with CAD, tech, and circuit design teams to align layout schedules with overall project plans.
• Communicate complex layout design issues cross-functionally.

Requirements

• 10+ years of experience in analog layout design and 3+ years in management.
• Deep understanding of layout methodology from initial chip planning to tape-out.
• High proficiency in LVS and DRC debugging, specifically interpreting Calibre reports.
• Proficiency in Synopsys or Cadence layout entry tools.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).
• Excellent verbal and written communication skills with experience in conflict resolution.

Nice to have

• Experience with advanced process technology and FinFET.
• Programming skills in Skill, TCL, or Perl.

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Environment focused on shared collaboration, transparency, and inclusivity.
• Dedicated resources and tools to support professional growth and success.