Senior Analog Layout Engineer (Semiconductor)

TL;DR

Senior Analog Layout Engineer (Semiconductor): Designing and verifying high-speed or precision analog circuits for data infrastructure with an accent on floorplanning and iterative debugging. Focus on utilizing Cadence Virtuoso to deliver complex IPs and collaborating with global teams to ensure designs meet rigorous specifications.

Location: Singapore

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Run simulations and verifications using Cadence Virtuoso to refine and debug designs iteratively.
• Own the complete development lifecycle, from initial floorplanning and layout to verification, delivery, and support.
• Collaborate closely with designers and global teams across Argentina, the U.S., and Europe.
• Scale ownership from individual cells and functional blocks to higher-level macros and full chips.
• Act as a technical mentor and key contributor during project lifecycle meetings.

Requirements

• Degree in Electrical Engineering (undergraduate or graduate).
• Proficiency with CAD tools for implementation and microelectronic layers.
• Proven track record of delivering high-speed or precision analog circuits in multiple process nodes.
• Strong communication skills for presenting technical solutions to global teams across different time zones.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Environment characterized by shared collaboration, transparency, and inclusivity.
• Opportunity to work on purposeful, enduring innovation within a global team.
• Support for continuous learning and professional growth.

Hiring process

• Interviews focusing on individual experience, thought process, and real-time communication.
• Strict prohibition of AI tools (e.g., ChatGPT, Copilot) during the interview process; use results in disqualification.