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Senior Manager, Analog Layout Design (Semiconductor)

136Β 620 - 204Β 700$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior/lead
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

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TL;DR

Senior Manager, Analog Layout Design (Semiconductor): Leading and growing a team of analog layout engineers to deliver high-quality physical layout solutions for high-speed, mixed-signal, and advanced technology integrated circuits. Focus on technical leadership, project execution, and methodology development to ensure successful tapeouts across multiple FinFET and CMOS process nodes.

Location: Must be based in Santa Clara, CA

Salary: $136,620–$204,700 per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential infrastructure technology for data centers, cloud, AI, and networking architectures.

What you will do

  • Lead, mentor, and develop a high-performing team of analog layout engineers.
  • Own layout execution planning, resource allocation, and schedule management across multiple projects.
  • Provide technical guidance for analog and mixed-signal layout implementation in advanced technologies like FinFET and CMOS.
  • Drive improvements in layout methodologies, automation, and verification flows.
  • Collaborate with cross-functional teams including circuit design, physical design, and CAD to ensure design integrity.
  • Support silicon bring-up, root-cause analysis, and post-tapeout issue resolution.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field.
  • 10+ years of analog layout design experience, including 3+ years in a leadership role.
  • Strong expertise in advanced analog, high-speed, and mixed-signal layout design (SerDes, PLLs, ADCs/DACs, etc.).
  • Proficiency with industry-standard EDA tools such as Cadence Virtuoso and Calibre.
  • Proven track record of multiple successful tapeouts in advanced FinFET process nodes.
  • Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

  • Comprehensive benefits package including financial well-being, family support, and health resources.
  • Employee stock purchase plan with a 2-year look back.
  • Focus on long-term innovation and professional growth within a global engineering organization.
  • Supportive environment prioritizing mental and physical health.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’