Physical Design Senior Staff Engineer (ASIC)

TL;DR

Physical Design Senior Staff Engineer (ASIC): Performing physical implementation of complex integrated circuits with an accent on timing closure and noise sign-off. Focus on developing timing and logic ECOs and optimizing end-to-end flows for high-performance processor chips.

Location: Westborough, MA

Salary: $138,000 - $168,000 per year

Company

hirify.global is a semiconductor solutions provider developing essential data infrastructure building blocks for enterprise, cloud, AI, and carrier architectures.

What you will do

• Execute physical implementation of complex integrated circuits (ICs).
• Customize and support global timing and noise sign-off flows using industry-standard EDA tools.
• Own timing closure for specific chip portions or the full chip.
• Develop and implement timing and logic ECOs via automated and manual methods.
• Collaborate with RTL design teams to resolve congestion and timing issues.
• Evaluate and test new vendor tools to improve CAD activities.

Requirements

• Master's degree in Electrical/Electronic Engineering, Computer Science, or a related field.
• 2+ years of experience in Static Timing Analysis (STA) or Place and Route (PnR).
• Proficiency with Synopsys or Cadence tools for evaluating timing results.
• Experience with SDC commands, I/O timing, clock definitions, and crosstalk analysis.
• Scripting skills in PERL, TCL, PYTHON, or UNIX shell.
• Must be eligible to access export-controlled information under U.S. law.

Culture & Benefits

• Competitive compensation package and comprehensive benefits.
• Collaborative, transparent, and inclusive work environment.
• Strong emphasis on professional growth and development tools.

Hiring process

• Interviews focus on individual experience, thought process, and communication skills.
• Use of AI tools (ChatGPT, Copilot, etc.) during interviews is strictly prohibited and results in disqualification.