Digital Implementation and Signoff, Principal AE (Semiconductor)

TL;DR

Principal Digital Implementation and Signoff AE (Semiconductor): Supporting leading-edge customers in deploying Synthesis, P&R, and Signoff technologies with an accent on meeting PPA targets and accelerating design closure. Focus on driving technical evaluations, collaborating with R&D to influence next-generation products, and optimizing backend digital design flows.

Location: San Jose, CA

Salary: $123,200 – $228,800

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools for the semiconductor industry.

What you will do

• Provide technical support to customers in Backend Digital Design Implementation and Signoff, including Place and Route and timing/power signoff.
• Guide customers on utilizing hirify.global technologies to achieve design goals and maintain project schedules.
• Conduct technical presentations, product demonstrations, and drive technical evaluations and benchmarks.
• Collaborate with R&D to enhance tools and methodologies based on customer requirements.
• Develop and augment design flows using Tcl and other programming skills to improve efficiency.
• Capture and apply best practices from benchmarks to increase the success rate of future engagements.

Requirements

• 10+ years of industry Physical Design experience.
• BS degree in Computer Science, Electrical Engineering, or a related field.
• Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
• Experience with IC digital implementation flows and backend EDA tools (P&R, IR Drop, timing/power closure).
• Experience working with advanced nodes 10nm and below.
• Proficiency in scripting languages such as Tcl, Perl, or Python.

Nice to have

• MS degree in Computer Science, Electrical Engineering, or a related field.
• Experience with front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking.
• Prior experience with hirify.global tools (Genus, Innovus, Conformal, Tempus, Modus, Voltus) or competitors (ICC, ICC2, DC, Primetime).
• Experience with advanced nodes 5nm and below.

Culture & Benefits

• Competitive incentive compensation structure including bonuses and equity.
• Comprehensive health benefits including medical, dental, and vision plan options.
• Retirement planning with a 401(k) plan and employer match.
• Employee stock purchase plan (ESPP).
• Paid vacation and paid holidays.