Physical Verification Engineer (Semiconductors)

TL;DR

Physical Verification Engineer (Semiconductors): Providing technical support for layout verification and parasitic extraction for hirify.global Foundry Services customers with an accent on advanced CMOS processes (22nm and below). Focus on resolving complex physical design challenges, optimizing verification flows (DRC, LVS, ERC, PERC), and ensuring successful customer tape-outs.

Location: Hybrid (Must be based in the US: Phoenix, AZ; Santa Clara, CA; or Hillsboro, OR). US Citizenship required.

Salary: $128,880 – $245,160 USD

Company

hirify.global Foundry is a systems foundry delivering cutting-edge silicon process and packaging technology leadership for the AI era.

What you will do

• Provide comprehensive technical support to customers on layout verification and parasitic extraction challenges.
• Collaborate with internal teams, IP providers, and EDA vendors to resolve design rule and extraction issues.
• Optimize physical verification flows for advanced CMOS processes (22nm and below).
• Create application notes, technical documentation, and deliver technical training presentations.
• Lead the implementation and optimization of DRC, LVS, ERC, and PERC methodologies.
• Guide customers through advanced process technology adoption to ensure successful design tape-outs.

Requirements

• US Citizenship is required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a STEM field.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience with layout verification and parasitic extraction EDA tools.
• Proficiency in scripting languages such as Python, Perl, Tcl, or shell scripting.

Nice to have

• Active US Government Security Clearance (Secret level or higher).
• Post-graduate degree in a STEM field.
• Experience with StarRC, Quantus, or xACT extraction tools.
• Experience with ICV, Calibre, or Pegasus EDA tools and rule deck coding.
• Customer-facing experience and technical leadership of engineering teams.

Culture & Benefits

• Hybrid work model splitting time between on-site and off-site.
• Competitive compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation benefits.
• Opportunity to work with cutting-edge technologies impacting national security.
• Professional development in advanced foundry services and verification methodologies.