Senior Physical Design Engineer (ASIC)

TL;DR

Senior Physical Design Engineer (ASIC): Implementing industry-leading mixed-signal SOCs for consumer markets with an accent on RTL to GDS2 physical implementation. Focus on driving the full design flow to closure and tapeout, including synthesis, timing closure, and power analysis.

Location: Must be based within commutable distance of Edinburgh, UK

Company

hirify.global is a leader in mixed-signal processing, delivering innovative solutions for top consumer brands with a focus on inclusive culture and engineering excellence.

What you will do

• Manage all aspects of RTL to GDS2 physical implementation for complex ASIC projects.
• Collaborate with Digital Design, Analogue Layout, and DFT teams to ensure high-quality results.
• Participate in project scoping and planning activities.
• Develop and improve P&R methodologies.
• Perform debug and analysis of designs, libraries, and technology files.

Requirements

• Degree in Electrical Engineering or related discipline.
• Proven industry experience in a Physical Design position.
• Expertise in deep sub-micron ASIC implementation including synthesis, floorplanning, and timing closure.
• Proficiency with industry-standard EDA tools like Synopsys Design Compiler, Primetime, and Cadence Innovus.
• Strong scripting skills for flow automation.
• Must be able to access technical data without an export license (no sponsorship available).

Culture & Benefits

• Award-winning inclusive and fair workplace culture.
• Hybrid work model with 2+ days in-office.
• Opportunities to work on cutting-edge consumer technology.
• Focus on professional growth and career development.