Memory System Designer and Place and Route Engineer (Semiconductor)

TL;DR

Memory System Designer and Place and Route Engineer (Semiconductors): Designing and implementing large memory blocks and subsystems with an accent on RTL implementation and physical design closure. Focus on optimizing timing, DRC, LVS, and EM/IR to ensure high-performance memory architectures.

Location: USA-Mendota Heights-Northland

Salary: $108,000 - $172,800

Company

A global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Architect and design high-performance memory subsystems.
• Implement RTL for subsystem designs using Verilog.
• Perform physical design including place and route operations.
• Achieve design closure across timing, DRC, LVS, and EM/IR.
• Execute gate netlist synthesis and validate using logical equivalency checkers.

Requirements

• Bachelor's degree in Electrical Engineering.
• Minimum 8 years of relevant design experience.
• Proficiency in Verilog RTL coding and debugging.
• Expertise in place and route and design closure tools (STA, DRC, EM/IR).
• Ability to write automation scripts in Python.
• Must be based in or eligible to work in the USA.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(K) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company holidays.
• Employee Assistance Program (EAP).