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3 часа назад

Senior Staff Design Verification Engineer (Memory Sub-System)

134 390 - 201 300$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Design Verification Engineer (Memory Sub-System): Designing and executing verification plans for high-speed memory interfaces including DDR, LPDDR, and HBM with an accent on UVM/SystemVerilog environments and protocol-level validation. Focus on developing test benches, performing coverage-driven verification, and ensuring spec compliance for advanced custom chips.

Location: Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

hirify.global provides essential semiconductor solutions for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3).
  • Build and enhance UVM/SystemVerilog-based verification environments.
  • Develop test benches, sequences, and checkers for functional and performance validation.
  • Perform protocol-level verification for memory controllers and PHY interfaces.
  • Analyze and debug simulation failures to identify root causes and drive resolution.
  • Collaborate with design, architecture, and firmware teams to ensure coverage closure and spec compliance.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5-10 years of experience in ASIC/SoC verification.
  • Strong knowledge of DDR, LPDDR, or HBM protocols and architecture.
  • Expertise in SystemVerilog and UVM methodology.
  • Proficiency in debugging complex verification issues using industry-standard tools.
  • Must be eligible to access export-controlled information under U.S. export control laws (EAR).

Nice to have

  • Knowledge of JEDEC standards for DDR/LPDDR/HBM.
  • Experience with assertion-based verification (SVA).
  • Exposure to performance modeling, traffic generation, or emulation platforms (Palladium, Veloce).
  • Scripting skills in Python, Perl, or Shell.
  • Experience with low-power verification (UPF).

Culture & Benefits

  • Employee stock purchase plan with a 2-year look-back.
  • Comprehensive family support programs to balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards to celebrate milestones.

Hiring process

  • Real-time interviews evaluating experience, thought process, and communication.
  • Strict prohibition of AI tools (ChatGPT, Copilot, etc.) during interviews; use results in disqualification.

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