Senior Testchip SoC Physical Design Engineer (Semiconductor)

TL;DR

Senior Testchip SoC Physical Design Engineer (Semiconductor): Developing layout design methodologies and driving full-chip SoC integration for advanced testchip vehicles with an accent on hierarchical layout specifications and design convergence. Focus on executing tactical plans for physical design convergence, resolving verification issues, and improving tool/flow methodologies for next-generation process nodes.

Location: Hybrid; Must be based in the US (Hillsboro, OR; Santa Clara, CA; or Austin, TX)

Salary: $141,910.00 - 200,340.00

Company

hirify.global Foundry's Design Technology Platform organization focusing on next-generation semiconductor innovation and high-volume manufacturing readiness.

What you will do

• Develop layout design methodology for testchips in next-generation process nodes.
• Collaborate with Process Integration, Yield, and QnR to define critical design features for lead vehicles.
• Establish and maintain hierarchical layout design specifications for correct-by-construction integration.
• Execute tactical plans to converge hierarchical SoC layout design within aggressive schedules.
• Drive physical design convergence, prepare layout hierarchy for tape-in, and resolve verification issues.
• Partner with tool/flow owners and vendors to improve methodologies and productivity.

Requirements

• Master's degree in electrical engineering or a related field.
• Minimum 5 years of experience in physical/layout design for advanced technology nodes.
• Proficiency with layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler.
• Deep knowledge of design rules and layout constraints in advanced semiconductor processes.
• Experience with floorplanning, hierarchical design integration, and layout verification/debug.
• Must be eligible to work in the United States.

Nice to have

• Experience defining testchip/product design from concept to execution commit.
• Experience negotiating design features with foundry teams.
• Project management skills for coordinating the design cycle from feature definition to tape-in.
• Previous experience working within a semiconductor foundry.

Culture & Benefits

• Work on cutting-edge semiconductor technologies shaping the future of computing.
• Hybrid work model allowing a split between on-site and off-site work.
• Comprehensive benefits package including health, retirement, and vacation.
• Opportunities for technical leadership and professional career growth.
• Collaborative environment working with industry-leading experts.