Physical Design Manager (ASIC)

TL;DR

Physical Design Manager (ASIC): Contribute to physical design and methodology development for high-performance processor and accelerator silicon in leading-edge CMOS processes with an accent on timing closure, power optimization, and scalability. Focus on hands-on execution for AI training/inference, cloud compute, and high-bandwidth networking applications, driving closure strategies and resolving complex issues at block, partition, or subsystem levels.

Onsite at hirify.global’s Westborough, Massachusetts location. Remote or hybrid opportunities not offered. Relocation assistance provided for qualified candidates. May require U.S. export control eligibility; non-U.S. citizens subject to license review.

Salary: $185,900 - $275,170 per annum (USD)

Company

Semiconductor solutions provider powering data infrastructure for enterprise, cloud, AI, and carrier architectures with custom processors and ASICs.

What you will do

• Serve as primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems.
• Perform hands-on physical design, timing analysis, late-stage debug, and convergence.
• Define and drive closure strategies, acting as technical escalation point.
• Lead and mentor small team of PD engineers as player-coach, providing prioritization and execution guidance.
• Coordinate with STA, RTL, CAD, and program teams to resolve issues.
• Support hiring, onboarding, and communicate status/risks to leadership.

Requirements

• Bachelor’s in CS/EE or related + 10-15 years experience (or Master’s/PhD + 5-10 years) in physical design.
• Principal-level expertise delivering timing-closed ASICs/SoCs.
• Deep knowledge of timing analysis/closure, SI, CDC, LVF, POCV methodologies.
• Proficiency with PD/STA tools (e.g., Synopsys PrimeTime), scripting, UNIX/Linux.
• Experience leading PD engineers hands-on as player-coach.
• Strong communication for technical tradeoffs and cross-functional coordination.

Nice to have

• Experience owning full-chip or large-subsystem PD/timing closure.
• Familiarity with timing methodology/flow development.
• Working with multi-site/global teams.
• Balancing FTE/contractor resources.

Culture & Benefits

• Comprehensive benefits: financial well-being (employee stock purchase), family support, mental/physical health resources, recognition awards.
• Opportunity to grow into broader leadership while staying technically engaged.
• Focus on purposeful innovation in data infrastructure.