Назад
Company hidden
1 день назад

Principal Physical Design/Implementation Engineer (Semiconductor)

158 600 - 237 600$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Principal Physical Design/Implementation Engineer (Semiconductor): Architecting and leading the development of physical design methodologies and automation flows for complex SubSystems with an accent on RTL-to-GDSII implementation and timing closure. Focus on delivering production-quality SoC designs on aggressive schedules using the latest process nodes (2nm, 3nm, 5nm).

Location: Onsite in Santa Clara, CA or Irvine, CA. Relocation provided.

Salary: $158,600 - $237,600 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

  • Architect and lead next-generation physical design methodologies and automation flows for complex subsystems.
  • Drive RTL-to-GDSII implementation, including synthesis, floor planning, place and route, clock tree synthesis, and timing closure.
  • Collaborate with DFT and RTL teams to perform DFT insertion, close timing at the SoC level, and implement ECOs or bug fixes.
  • Deliver reference floorplans and fully synthesized, timing-closed subsystem partitions to the SoC team.
  • Mentor and coach senior and junior engineers to foster technical growth and promote organization-wide best practices.
  • Evaluate and drive the adoption of emerging EDA tools and technologies in partnership with CAD teams and vendors.

Requirements

  • Bachelor's degree in CS, EE, or related field with 10-15 years of experience (or Master's/PhD with 5-10 years).
  • Deep domain expertise in SoC architecture, processor cores, memory, and PCIE/CXL.
  • Extensive experience in synthesis, floor planning, P&R, and timing closure for large subsystems.
  • Proficiency in Verilog and conducting static quality checks of implemented RTL.
  • Experience working with leading foundries and advanced process nodes (2nm, 3nm, 5nm).
  • Hands-on experience with interpretive languages such as Perl or Python.

Culture & Benefits

  • Comprehensive benefits focusing on financial well-being, family support, and mental/physical health.
  • Employee stock purchase plan with a 2-year look-back.
  • Family support programs designed to balance work and home life.
  • Robust mental health resources and recognition/service awards for milestones.
  • Supportive environment for professional growth and leadership.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →