Senior Principal Engineer, Chip Lead (Photonic Fabric)

TL;DR

Senior Principal Engineer, Chip Lead (Photonic Fabric): Leading the end-to-end development of heterogeneous photonic chiplets combining high-speed electrical ICs and photonic integrated circuits with an accent on mixed-signal SoC design and advanced co-packaging. Focus on driving micro-architecture, RTL development, and system-level validation to eliminate data center interconnect bottlenecks for AI accelerators.

Location: Santa Clara, CA

Salary: $182,360 - $273,200 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, and AI architectures.

What you will do

• Own end-to-end product design spanning Electrical IC, Photonic IC, firmware stack, and advanced packaging.
• Lead micro-architecture and RTL development for Electrical ICs, including high-speed SERDES and digital subsystems such as UALink and UCIe.
• Collaborate with verification, physical design, and packaging teams on floorplanning, timing, power, and physical verification closure.
• Drive DFT strategy for digital and analog SERDES and partner with photonics teams to define PIC architecture and control schemes.
• Lead cross-functional teams through ATE enablement, silicon bring-up, and system-level validation, including root-cause analysis across silicon and optics.
• Mentor senior engineers and communicate technical status, risks, and tradeoffs to executive leadership.

Requirements

• Bachelor's degree with 15+ years of professional experience, or Master's/PhD with 8-12 years of experience in related fields.
• Deep experience in ASIC/SoC development with proven end-to-end chip ownership.
• Expertise in Micro-architecture, RTL design, high-speed analog SERDES, physical design sign-off, and DFT.
• Proven track record in advanced packaging, chiplet-style integration, and post-silicon bring-up.
• Must be eligible to access export-controlled information under U.S. export control laws (EAR).
• Strong ability to drive alignment across cross-functional teams in a matrixed environment.

Nice to have

• Prior experience delivering high-speed I/O and/or optical products into production.
• Experience acting as a Chip Lead, SoC Architect, or System-Level Technical Lead.

Culture & Benefits

• Financial well-being programs, including an employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate professional milestones.