Sr. ASIC Physical Design Engineer

TL;DR

Sr. ASIC Physical Design Engineer (SoC): Implement physical design at large SoC block level from RTL to GDSII with an accent on floorplanning, clock networks, place & route, power grid, and IP integration. Focus on optimizing timing, area, power constraints, generating ECOs, and achieving sign-off for 7nm+ tapeouts.

Location: Hybrid (average 2 days per week from HPE office, US-based)

Salary: USD 153,500 - 310,500 (United States, California)

Company

Global edge-to-cloud company helping organizations connect, protect, analyze, and act on data from edge to cloud.

What you will do

• Implement block-level physical design from RTL to GDSII, creating manufacturing-ready databases.
• Integrate IPs, sub-chips, and blocks at SoC level, collaborating with IP vendors and packaging team.
• Build floorplans with macro placement, power grid, clock networks, and static timing constraints.
• Perform place & route, optimization for timing/area/power, repeater/feedthrough insertion.
• Generate ECOs for timing/SI/EM/IR fixes, integrate DFT, and run verification flows (LVS/DRC/ERC/ANT).
• Collaborate with architecture, frontend, DV, and package teams for successful tapeouts.

Requirements

• BS in electrical/computer engineering + 3+ years or MS + 2+ years in block/full-chip physical design
• Deep experience in large SoC physical design: synthesis, floorplanning, PnR, CTS, power/clock networks.
• Knowledge of SoC architecture, Verilog, physical verification (LVS/DRC/ERC/ANT).
• Custom place & route, Linux shell scripting (Perl/TCL/Python).
• Real 7nm+ tapeout experience with successful signoff
• Strong problem-solving, debugging, and teamwork skills.

Nice to have

• Exposure to 2.5D/3D packaging, high-performance/large chip design, DFT.

Culture & Benefits

• Comprehensive health, financial, emotional wellbeing benefits.
• Personal/professional development programs for career growth.
• Unconditional inclusion, flexibility for work/personal needs, bold collaborative moves.