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18 часов назад

Senior Staff Analog Circuit Design Engineer (SerDes)

164 470 - 361 480$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Senior Staff Analog Circuit Design Engineer (SerDes): Design and implement advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications with an accent on high-performance analog blocks and subsystems. Focus on definition, verification, post-silicon validation, performance optimization, and cross-functional collaboration.

Location: Hybrid model requiring time on-site at hirify.global sites in US (California: Santa Clara, Folsom; Oregon: Hillsboro)

Salary: $164,470 - $361,480

Company

hirify.global's Central Engineering Group builds scalable engineering solutions across product enablement, custom ASIC, and foundry enablement.

What you will do

  • Design and implement advanced analog and mixed-signal circuits for 112G/224G SerDes
  • Define, design, and verify high-performance analog blocks and subsystems
  • Conduct post-silicon validation and performance optimization
  • Provide guidance to layout engineers and mentor junior designers
  • Collaborate with system architects, digital designers, and layout teams
  • Contribute to technical discussions, design reviews, and innovative high-speed interconnect solutions

Requirements

  • Bachelor’s degree in Electrical Engineering, Electronics Engineering, or STEM field
  • 2+ years in analog/mixed-signal circuit design for high-speed SerDes or similar
  • Experience in PLL, CDR, CTLE, DFE, ADC, LDO, Ref Gen, or TX design
  • Core analog principles: noise, linearity, matching, stability
  • Advanced FinFET CMOS processes
  • Analog design tools: Cadence Virtuoso/ADE, HSPICE or equivalent

Nice to have

  • Ph.D. in Electrical/Electronics Engineering or STEM
  • Transmitter/receiver design, CDR loops, equalization
  • High-speed standards: PCIe 6.0, 800G Ethernet, JESD, PCIe Gen4/5, 100G/400G Ethernet
  • Verilog-A modeling, MATLAB, automation scripting (Python, Tcl)
  • Signal integrity, channel modeling, system-level link analysis

Culture & Benefits

  • Competitive pay, stock bonuses, health, retirement, vacation benefits
  • Hybrid work model splitting on-site and off-site time
  • Collaborative, cross-functional team environment
  • Opportunities for technical reviews, mentoring, and innovation

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