Senior Staff Design Engineer (Memory Subsystem)

TL;DR

Senior Staff Design Engineer (Memory Subsystem): Designing and implementing production-ready IP subsystems for DDR, LPDDR, and HBM to power advanced custom chips for hyperscale cloud and AI with an accent on RTL implementation and micro-architecture definition. Focus on translating architecture requirements into robust RTL designs and ensuring seamless integration within ARM-based SoC environments.

Location: Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Lead DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration.
• Collaborate with Architecture teams to translate requirements into high-performance RTL designs.
• Partner with Design Verification, Physical Design, and DFT teams for test-plan reviews and coverage closure.
• Support silicon bring-up and post-silicon debug in coordination with firmware and validation teams.
• Drive design quality improvements, coding best practices, and IP reuse across projects.
• Mentor junior designers and provide technical leadership within the memory design domain.

Requirements

• Bachelor's or Master's degree in Electronics/Electrical Engineering with 8-10+ years of RTL design experience.
• Proven track record of delivering complex DDR, LPDDR, or HBM controllers from architecture to RTL closure.
• Strong expertise in System Verilog, Verilog, and JEDEC specifications.
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Solid grasp of Clocking, Resets, CDC/RDC, and low-power optimization techniques.
• Must be eligible to access export-controlled information under U.S. export control laws.

Nice to have

• Experience with end-to-end DDR/HBM subsystem RTL design execution and sign-off.
• Ability to design high-performance, low-latency data paths with complex coherency and error mechanisms.
• Proficiency in debugging functional and performance issues at the subsystem and SoC levels.
• Familiarity with post-silicon bring-up and debug methodologies.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Comprehensive family support programs to balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards for career milestones.
• Inclusive environment promoting growth, learning, and leadership.