Principal Design Engineer

TL;DR

Principal Design Engineer (RTL/FPGA): Designing, developing, and productizing protocol products like PCIe and advanced Ethernet for hirify.global's flagship emulation and prototyping line with an accent on logic RTL design, UVM verification, board design, and documentation. Focus on solving complex protocol and system integration issues, electrical and timing closure challenges, and RTL design/verification methodologies.

Location: Shanghai

Company

Leader in electronic design automation (EDA) tools for IC design and verification.

What you will do

• Work on hirify.global's flagship emulation and prototyping product line.
• Design, develop, modify, and productize protocol products like PCIe and advanced Ethernet.
• Perform RTL design, UVM-based verification, board design/debug, and documentation as an individual contributor.
• Tackle complex problems in protocol/system integration, electrical/timing closure, and RTL methodologies.

Requirements

• MSEE or equivalent with experience in logic design and debug.
• Excellent written and verbal communication skills.
• RTL design experience using Verilog and RTL verification tools/flows.
• Experience in FPGA design for Xilinx products strongly recommended.
• UVM verification experience desired.
• Experience with scripting languages like Perl, TCL, C-shell desired.