Digital Design RTL Engineer (Semiconductor)

TL;DR

Digital Design RTL Engineer (SystemVerilog): Designing and optimizing high-performance RTL for advanced process nodes with an accent on SoC integration and PPA optimization. Focus on delivering high-quality RTL in 5nm and below nodes, managing clock domain crossing (CDC) analysis, and implementing low-power design techniques.

Location: Onsite in Fort Collins, CO or San Jose, CA (USA)

Salary: $91,000 - $146,000

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Operate autonomously to take designs from initial specification through timing closure and physical design hand-off.
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet milestones.
• Develop high-quality SystemVerilog RTL for advanced process nodes (5nm and below).
• Implement PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques.

Requirements

• BSEE required; MSEE or PHD preferred.
• 5+ years of industry experience focusing on SoC integration.
• High proficiency in SystemVerilog.
• Experience with LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching.
• Discretionary annual bonus and competitive new hire equity grants with annual awards.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Company paid holidays, paid sick leave, and vacation time.