Senior ASIC Physical Design Engineer

TL;DR

Senior ASIC Physical Design Engineer (SoC): Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification with an accent on timing closure and optimization across multiple corners and modes. Focus on achieving power, performance, and area goals, collaborating with front-end and verification teams, and supporting chip-level integration and tapeout for space-qualified ASICs.

Location: United States - Remote. Must be a U.S. Person (U.S. citizen, permanent resident, or protected individual) per ITAR export control regulations

Salary: $170,000 – $250,000 + equity

Company

Building the largest and highest-power satellites ever flown for missions from LEO to deep space, backed by leading investors and with signed contracts across commercial and US government customers.

What you will do

• Execute full physical design flow for complex SoC blocks and top-level integration using industry-standard tools.
• Perform timing closure, optimization, and physical verification across multiple corners and modes.
• Collaborate with front-end, verification, DFT teams, and external service providers to ensure clean handoffs and schedule alignment.
• Develop scripts and automation to improve flow efficiency and support sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
• Assist in chip-level integration, ECOs, tapeout preparation, and production through spaceflight.
• Contribute to methodology development, tool evaluation, and flow documentation.

Requirements

• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field
• 5–10 years of experience in ASIC physical design for complex SoCs
• Hands-on experience with Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent
• Strong understanding of timing analysis, power optimization, physical verification, hierarchical/flat methodologies
• Working knowledge of DFT, UPF/CPF, ECO implementation
• Strong problem-solving skills and ability to work cross-functionally

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs
• Experience with chip-package co-design, advanced packaging (2.5D/3D), FinFET, Gate-All-Around technologies
• Familiarity with TSMC sign-off and physical design service vendor management
• Experience in cross-functional, geographically distributed teams

Culture & Benefits

• Comprehensive benefits including paid time off, medical/dental/vision coverage, life insurance, paid parental leave
• Equity in the company
• Fast-paced environment in a Series C space startup with multiple launches planned through 2026-2027
• Collaborative team developing state-of-the-art mixed-signal SoCs for rapidly manufactured satellites