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19 часов назад

Fullchip Floorplan Design Engineer (ASIC)

105 650 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Fullchip Floorplan Design Engineer (ASIC): Designing top-down SoC floorplans and optimizing IP placement for latency and area with an accent on power grid creation, multi-power domain planning, and die-area estimation. Focus on driving physical convergence, managing metal stacks, and implementing industry-standard EDA flows for high-performance silicon products.

Location: Hybrid (USA: Fort Collins, Beaver Brook, Hillsboro, Folsom, Austin)

Salary: $105,650 - $200,340

Company

hirify.global is a global leader in designing and manufacturing silicon products that power data centers, AI-accelerated systems, and connected devices.

What you will do

  • Execute top-down SoC floorplanning, including IP placement, partitioning, and PG grid creation.
  • Define optimal physical dimensions and estimate die-area based on technology selection and product costs.
  • Supervise physical placement and channel planning for sub-systems to ensure area and schedule convergence.
  • Collaborate with clock and power delivery teams to optimize metal allocation and block-level floorplans for APR.
  • Develop and refine methodologies and tools to streamline the physical design workflow.

Requirements

  • Bachelor's in Electrical/Electronics/Computer Engineering (3+ years exp) or Master's (2+ years exp).
  • 2+ years of experience with industry-standard EDA tools for floorplanning and APR.
  • Experience with multi-power domain designs and Synopsys Fusion Compiler.
  • Proficiency in TCL, Python, or Perl programming.
  • Experience with Calibre or ICV verification.
  • Must be based in the US to support the hybrid work model.

Nice to have

  • Deep knowledge of SoC requirements including voltage/clock domains, thermal management, and Die-to-Die interconnects.
  • Expertise in ICC2/FC, Place and Route flows, and Physical Design Verification.
  • Experience with large subsystem designs (20M+ gates) at frequencies exceeding 2GHz.
  • Understanding of UPF/CPF and low power static verification.

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation programs.
  • Hybrid work model allowing a split between on-site and off-site work.

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