Analog Layout Designer (Semiconductors)

TL;DR

Analog Layout Designer (Semiconductors): Designing block and IP level analog layouts for advanced nodes with an accent on SerDes, ADC/DAC, and PLL modules. Focus on floorplanning, top-level integration, and debugging DRC/LVS errors in deep sub-micron processes.

Location: Onsite in Irvine, CA, USA

Salary: $108,000 – $172,800 per year

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Perform independent block-level and IP-level analog layout design.
• Collaborate with circuit designers and the layout team to ensure design alignment.
• Develop floorplans and layouts for analog modules such as SerDes, ADC/DAC, and PLL.
• Handle top-level integration for advanced nodes.
• Debug and resolve DRC, LVS, and antenna errors.
• Implement analog layout concepts for deep sub-micron processes, managing ESD, latch-up, and EM.

Requirements

• Bachelor's degree.
• Minimum 8+ years of hands-on experience in Analog or RF layout.
• Strong understanding of fabrication processes and deep sub-micron layout concepts.
• Ability to provide onsite support in Irvine, CA.

Nice to have

• Experience with FinFet processes.
• Proficiency with Cadence tools.
• Experience with TSMC processes.

Culture & Benefits

• Discretionary annual bonus and competitive new hire equity grants.
• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid sick leave, vacation time, and company paid holidays.