9 дней назад
Digital IC Design Verification Engineer (Analog/Mixed-Signal)
147 000 - 220 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Digital IC Design Verification Engineer (Analog/Mixed-Signal): Designing and verifying display IC layouts for augmented reality eyewear with an accent on custom transistor-level layout, analog and mixed-signal circuits, and physical verification. Focus on automating design flows, executing DRC/LVS and parasitic extraction, and optimizing area, performance, power, and reliability.
Location: United States; hybrid work with an expectation to work in an office 4+ days per week
Base salary: $147,000–$220,000 annually in Zone C, $164,000–$246,000 in Zone B, or $173,000–$259,000 in Zone A. The position is also eligible for RSUs.
Company
develops chat, Specs augmented-reality eyewear, OS, Lens Studio, and other digital services designed to make computing and communication more human.
What you will do
- Design custom display IC layouts for AR products as part of a multidisciplinary electronics team.
- Perform cell and block layout for analog and mixed-signal circuits while meeting design rules and performance targets.
- Support IC floor planning and place-and-route activities for full-chip digital designs integrating digital and analog IP.
- Develop reusable scripts and methodologies to automate design flows and improve repeatability and efficiency.
- Execute parasitic extraction and tapeout verification, including DRC, ERC, and LVS, and iterate layout improvements.
- Prepare design documentation, contribute schedule and cost inputs, and present work in internal design reviews.
Requirements
- BSEE or equivalent relevant experience.
- 5+ years of directly applicable custom layout experience.
- Strong knowledge of transistor-level custom layout, matching techniques, and analog and mixed-signal design.
- Strong working knowledge of Cadence Virtuoso and Mentor/Siemens Calibre for layout, schematic, DRC, LVS, and extraction.
- Experience with TCL, SKILL, Perl, Python, or Shell scripting in a Linux environment.
- Understanding of signal integrity, reliability, EM, IR drop, foundry DFM requirements, and tapeout verification.
Nice to have
- Experience with 22nm and below CMOS foundry design rules.
- Experience with analog and memory layouts, including SRAM, PLLs, ADCs, DACs, amplifiers, IO, ESD, and latch-up designs.
- Knowledge of ASIC testing and characterization, digital design, and place-and-route principles.
- Strong technical documentation and verbal communication skills.
Culture & Benefits
- Default Together policy with in-person office collaboration expected 4+ days per week.
- Paid parental leave and comprehensive medical coverage.
- Emotional and mental health support programs.
- Compensation includes potential long-term equity through RSUs.
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