Senior Staff Engineer (Digital IC Design)

TL;DR

Senior Staff Engineer (Digital IC Design): Designing and optimizing post-RTL flows for high-performance SerDes PHY solutions with an accent on synthesis, timing closure, and DFT generation. Focus on delivering competitive IP solutions for data infrastructure and AI architectures, ensuring physical timing closure for 28nm and beyond.

Location: Hsinchu, Taiwan

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Manage post-RTL design flow including block and chip level synthesis, timing closure, and DFT generation.
• Improve design methodology and flow for SerDes IPs ranging from 10Gbps to 224Gbps.
• Collaborate with Analog and Digital design teams to deliver competitive IP solutions across all hirify.global product lines.
• Provide pre- and post-silicon support to product teams.
• Perform custom placement and routing for mixed-signal designs and manage top-level physical timing closure.

Requirements

• Master’s degree and/or PhD in EE, CS, or related fields.
• 6+ years of experience in post-RTL design, including synthesis and timing analysis.
• Proficiency in logic or physical synthesis using Synopsys or Cadence tools.
• Expertise in DFT generation, verification, and Static Timing Analysis using Primetime.
• Experience with physical design for 28nm and beyond.
• Strong Perl and Tcl scripting skills.

Nice to have

• Experience in low power design.
• Circuit level or custom design experience.
• Expertise in floorplanning, clock-tree synthesis, and power planning/analysis.
• Knowledge of signal integrity and physical verification.

Culture & Benefits

• Competitive compensation and comprehensive benefits package.
• Work environment characterized by shared collaboration, transparency, and inclusivity.
• Access to tools and resources for professional growth and development.