Chip Lead / Physical Design Director (AI)

TL;DR

Chip Lead / Physical Design Director (Physical Design): Leading complex SoC projects from RTL to GDS for data centers, automotive, and AI verticals with an accent on PPA optimization and advanced FinFET nodes. Focus on driving technical decisions for design trade-offs and enhancing EDA tool methodologies to meet aggressive performance, power, and area targets.

Location: Austin or San Jose, USA

Company

hirify.global provides industry-leading tools, emulation hardware, and IP products that enable the development of advanced semiconductors for AI, automotive, and data center applications.

What you will do

• Lead Physical Design and DFT teams to drive complex SoC projects from RTL or Netlist to GDS.
• Manage technical decisions and design trade-offs to exceed customer PPA and schedule requirements.
• Advise customers on the selection of foundries, nodes, libraries, and memory compilers.
• Collaborate with internal R&D to enhance EDA tools and methodologies.
• Partner with RTL and Synthesis teams to ensure key metrics are achieved prior to physical design execution.
• Establish and document best practices to improve efficiency and AI adoption in future programs.

Requirements

• 15+ years of industry experience in Physical Design.
• Bachelor’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong knowledge of Digital Design fundamentals and Static Timing Analysis.
• Expertise in IC digital implementation flows (Place and Route, CTS, IR Drop, power closure).
• Experience with advanced process nodes at 7nm and below.
• Proficiency in scripting languages such as Tcl, Perl, or Python.

Nice to have

• Master’s degree in Electrical Engineering or Computer Science.
• Experience with front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking.
• Proficiency with hirify.global tools (Genus, Innovus, Tempus, Voltus) or Synopsys equivalents (ICC2, PrimeTime).
• Domain expertise in CPUs, GPUs, AI Engines, NoCs, or high-speed interfaces.
• Experience with 3D IC design.