Senior Digital Design Engineer

TL;DR

Senior Digital Design Engineer (SoC): Develop and implement digital IP and logic designs for complex Mixed-Signal SoCs with an accent on USB2, eUSB2, Type-C, USBPD, and related standards. Focus on micro-architecture, RTL coding in Verilog/SystemVerilog, verification, synthesis, STA, and DFT to meet timing, area, and power targets.

Location: Chandler office (Arizona), minimum 3 days per week full-day presence; willing to relocate to Phoenix Metro area

Company

World leader in secure connectivity solutions for embedded applications in automotive, industrial & IoT, mobile, and communication infrastructure markets.

What you will do

• Understand standards (USB2, eUSB2, TypeC, USBPD, TCPCI, BC1.2, I2C, SPI, SPMI) and micro-architect features for SoC products.
• Develop high-quality, area-optimal, low-power RTL designs using Verilog/SystemVerilog.
• Conduct IP-level verification, including testbench development, simulation, and debugging.
• Collaborate with architects, analog designers, test engineers, and software team on integration.
• Participate in synthesis, STA, formal verification, and DFT implementation.
• Generate documentation, participate in reviews, and troubleshoot issues.

Requirements

• Master's degree (MSEE) with focus on Digital Design, RTL coding, FPGA, Computer Architecture, Digital Verification
• 3-8 years experience in Digital Design & Architecture
• Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week in Chandler office
• Excellent problem-solving, teamwork, planning, organizing, attention to detail, and communication skills

Culture & Benefits

• Online and offline learning opportunities for core and professional skills development.
• Commitment to sustainability, diversity, inclusion, and equality.
• Inclusive work environment without tolerance for racism, discrimination, or harassment.