Senior DFT Engineer

TL;DR

Senior DFT Engineer (Mixed-Signal SoCs): Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan with an accent on RTL-level insertion, ATPG flows, and low-power methodologies. Focus on coverage closure, pattern optimization, mixed-signal integration, and silicon debug.

Location: United States - Remote. Must be a U.S. Person (citizen, permanent resident, or protected individual) per ITAR export control regulations

Salary: $170,000 – $250,000 + equity

Company

Building the largest and highest-power satellites for missions from LEO to deep space, backed by major investors with signed contracts.

What you will do

• Lead RTL-level DFT insertion, scan chain optimization, test point insertion, and low-power DFT methodologies.
• Develop and execute ATPG flows for stuck-at, transition, and path delay patterns, driving coverage closure and debug.
• Integrate DFT for mixed-signal blocks, including wrappers, analog test interfaces, and BIST solutions.
• Collaborate with RTL, DV, and PD teams for clean DFT integration, timing, and physical constraints.
• Drive DFT verification, signoff, and support silicon bring-up, yield analysis, and tester failure debug.
• Contribute to methodology development, automation, and flow improvements.

Requirements

• B.S. or M.S. in Electrical Engineering or related field
• 7+ years of experience in DFT for complex SoCs
• Strong hands-on experience with RTL DFT insertion (scan, compression, test points) and ATPG tools/flows.
• Deep understanding of scan architectures, compression, fault models, and coverage strategies.
• Experience with low-power DFT, mixed-signal integration, MBIST/LBIST, and IEEE 1149.x (JTAG).
• Strong debugging skills across RTL, gate-level, and silicon; scripting for automation.

Nice to have

• Experience with high-speed interfaces (SerDes) or RF/mixed-signal SoCs.
• Prior involvement in A0 silicon bring-up and yield ramp.
• Experience in cross-functional, geographically distributed teams; multi-voltage/power-aware DFT.

Culture & Benefits

• Comprehensive benefits: paid time off, medical/dental/vision coverage, life insurance, paid parental leave.
• Equity in the company.
• Fast-paced startup environment focused on groundbreaking space technology.
• Encourages non-traditional career paths and motivated individuals.