Physical Design Engineer, PnR (AI)

TL;DR

Physical Design Engineer, PnR (AI): Implementing high-performance partitions for an industry-leading AI SOC with an accent on the complete implementation flow from synthesis to tapeout. Focus on optimizing performance, power, and area while solving complex design challenges in silicon.

Location: Hybrid: Must be based in Austin, TX; Fort Collins, CO; or Santa Clara, CA (USA)

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing a high-performance RISC-V CPU and AI platform.

What you will do

• Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC.
• Close EM/IR and ensure UPF power intent is consistent with implementation.
• Drive LEC and physical verification signoff for partitions in coordination with methodology owners.
• Collaborate with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues.

Requirements

• Experience with synthesis and place-and-route flows, specifically using Synopsys Design Compiler, Fusion Compiler, and IC Compiler II.
• Ability to own a block or subsystem and partner on tapeout milestones with clear accountability.
• Must be eligible to access U.S. export-controlled technology (contingent upon citizenship or permanent residency status).

Nice to have

• Depth in UPF/multi-voltage power domains and SoC interface IP integration (e.g., I3C, UART).
• Experience in signoff breadth including DRC/LVS, EM/IR, and LEC/Formality.
• Knowledge of multi-clock/CDC-aware implementation and PLL/DLL integration.
• Expertise in DFT-aware physical implementation (OCC/MBIST).

Culture & Benefits

• Highly competitive compensation package and comprehensive benefits.
• Opportunity to work on cutting-edge AI silicon and RISC-V CPU technology.
• Collaborative environment valuing curiosity and a commitment to solving hard problems.