Advanced Packaging Process Engineer (AI)

TL;DR

Advanced Packaging Process Engineer (AI/Semiconductors): Driving advanced 2.5D and 3D chiplet packaging technology and reliability for next-generation AI/ML products with an accent on process integration and manufacturability. Focus on managing foundry/OSAT partnerships, optimizing yield, and solving complex mechanical risks like warpage and stress.

Location: Hybrid, based in Santa Clara, CA or Taipei City, TW. Candidate must be eligible to access U.S. export-controlled technology.

Compensation: $100k - $500k

Company

hirify.global is leading the industry in cutting-edge AI technology, developing high-performance RISC-V CPUs and an integrated AI platform.

What you will do

• Lead the implementation of advanced package technology for 2.5D/3D chiplet products, including technology selection and process integration.
• Act as the primary technical interface to foundries and OSATs to align design rules and drive yield optimization.
• Partner with design, reliability, and architecture teams to evaluate technical tradeoffs such as bump pitch and stack-ups.
• Define and track test vehicles and coordinate failure analysis (FA) to ensure product reliability.

Requirements

• MS/PhD in Materials, Mechanical, Electrical, Physics, or a related field.
• 5+ years of experience in advanced packaging for high-performance semiconductors.
• Hands-on expertise in 2.5D/3D flows such as CoWoS, FOCoS, EMIB, or FCBGA.
• Strong proficiency in reliability and root cause failure analysis for advanced packaging.
• Proven track record working with foundries/OSATs on NPI and production ramp.

Nice to have

• Experience using AI- and automation-driven methods for risk assessment and qualification planning.

Culture & Benefits

• Highly competitive compensation package.
• Collaborative environment with a commitment to solving hard problems.
• Exposure to leading-edge chiplet-based architectures for AI/ML.
• Equal opportunity employer.