Micro-Architect and RTL Designer (AI)

Location: Mountain View, California or remote within the United States

Salary: $200,000–$350,000 per year

Company

hirify.global is hiring for a fast-growing AI hardware company building a vertically integrated compute platform spanning silicon, systems, and software for large-scale machine learning workloads.

What you will do

• Develop scalable silicon architecture-to-design methodologies for blocks, subsystems, and full-chip designs.
• Own microarchitecture, major blocks, subsystems, or chip-level deliverables through sign-off-ready RTL.
• Define and review microarchitecture and design specifications.
• Drive design milestones including design freeze and tapeout.
• Optimize performance, power, area, timing, and overall design quality.
• Collaborate with verification, DFT, physical-design, and software engineers throughout development.

Requirements

• Concept-to-silicon experience developing ASIC or SoC subsystems or top-level functionality through production silicon.
• 4+ years of experience with SystemVerilog and RTL development workflows.
• Experience with Python, C, C++, or similar programming and scripting languages used in chip design.
• Production experience with microarchitecture and RTL design for CPUs, GPUs, AI/ML accelerators, high-performance computing, memory-management subsystems, or high-speed connectivity.
• Hands-on experience with synthesis, lint, RTL sign-off flows, and design testing.
• Strong understanding of performance, power, and area trade-offs in complex digital designs.

Nice to have

• Verification, emulation, or hardware emulation platform experience.
• High-speed I/O IP experience.
• Experience designing caches, buffers, crossbars, FIFOs, memory controllers, interconnects, DMA engines, or NoCs.
• Experience with compute pipelines, execution units, accelerator datapaths, or chip-level timing closure.

Culture & Benefits

• Full-time role focused on vertically integrated AI hardware development.
• Close collaboration across architecture, RTL, verification, DFT, physical design, and software.
• Opportunity to contribute to high-performance accelerator silicon from architecture through production sign-off.