2 дня назад
Member of Technical Staff - Design Verification (AI)
200 000 - 300 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Member of Technical Staff - Design Verification (AI): Developing and validating high-performance silicon for sustainable Generative AI across blocks, subsystems, full-chip, and system-level platforms with an accent on UVM, formal verification, memory technologies, and silicon milestones. Focus on creating testbenches, driving verification closure, and solving complex micro-architecture and high-performance compute validation challenges.
Location: Hybrid role based in the San Francisco Bay Area
Salary: $200,000–$300,000 annually
Company
represents an engineering-led company developing semiconductor and AI products for high-performance and sustainable Generative AI.
What you will do
- Contribute to verification methodology and execution across blocks, subsystems, full-chip designs, and system-level validation.
- Own verification execution at the subsystem and chip level.
- Create testbenches and drive verification progress and closure toward silicon milestones.
- Drive design verification from concept through silicon.
- Participate in silicon debugging and bring-up.
Requirements
- 5+ years of experience in design verification roles.
- Production experience with advanced verification methodologies, including UVM, AVB, or formal verification.
- Knowledge of LPDDR or HBM.
- Strong understanding of silicon microarchitecture and design concepts for high-performance computing, high-speed connectivity, and memory management.
- Ability to work in a hybrid setup in the San Francisco Bay Area.
Nice to have
- Familiarity with emulation and prototyping platforms and methodologies.
- Hands-on experience participating in silicon debugging and bring-up.
Culture & Benefits
- Work with engineers and industry veterans who have contributed to semiconductor and AI products.
- Contribute to high-performance and sustainable Generative AI silicon.
- Work on verification challenges spanning multiple design and validation levels.
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