Principal Physical Design Engineer (AI)

Location: San Francisco Bay Area, Mountain View, CA, Greater Boston, or San Jose, CA

Salary: $250,000–$400,000 per year

Company

hirify.global is partnering with a well-funded, early-stage AI hardware startup developing a next-generation inference platform that combines custom silicon with integrated software and systems engineering.

What you will do

• Own the complete physical design flow for major SoC blocks from floorplanning through final signoff.
• Drive place and route, clock tree synthesis, timing closure, power optimization, and physical verification.
• Develop AI-assisted implementation methodologies to improve productivity and accelerate tapeout schedules.
• Collaborate with architecture, RTL, verification, and software teams to optimize performance, power, and area.
• Work with EDA vendors and foundry partners to resolve implementation challenges and deliver production-ready silicon.

Requirements

• 8+ years of experience in physical design for complex, high-performance ASICs at advanced process nodes of 7nm or below.
• Deep expertise in synthesis, place and route, clock tree synthesis, timing closure, physical verification, and signoff.
• Hands-on experience with Cadence Innovus, Synopsys Fusion Compiler, or comparable implementation platforms.
• Experience with PrimeTime, Tempus, or equivalent industry-standard signoff tools.
• Proven ability to work cross-functionally with architects, RTL engineers, EDA vendors, and foundries.

Nice to have

• Experience with advanced packaging technologies such as 2.5D, 3D, or CoWoS.
• Experience with IR/EM analysis, thermal optimization, signal integrity, or DFT-aware implementation.

Culture & Benefits

• Work with a world-class engineering team experienced in semiconductor and AI companies.
• Help shape accelerator architecture and implementation from the earliest product stages.
• Meaningful equity participation.
• Medical, dental, and vision coverage.
• 401(k) and generous paid time off.