Назад
Company hidden
23 часа назад

Principal Analog Circuit Design Engineer (SerDes)

220 920 - 311 890$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Principal Analog Circuit Design Engineer (SerDes): Leading the design and validation of high-speed analog circuits for 112G and 224G SerDes applications with an accent on complex mixed-signal designs in advanced FinFET CMOS technology. Focus on implementing PLL, CDR, and ADC architectures to ensure robust performance for PCIe and Ethernet standards.

Location: Hybrid (US: Santa Clara, CA; Phoenix, AZ; Hillsboro, OR)

Salary: $220,920 - $311,890

Company

hirify.global's Central Engineering Group (CEG) is a data-driven organization building scalable engineering solutions across Product Enablement, Custom ASIC, and Foundry Enablement.

What you will do

  • Lead the design and validation of analog circuits for 112G and 224G SerDes applications.
  • Drive the technical definition and execution of complex analog and mixed-signal designs.
  • Provide technical direction and mentorship to layout and junior analog design engineers.
  • Collaborate with cross-functional teams, including systems, digital design, and test engineering.
  • Perform silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Requirements

  • Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
  • 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.
  • Proven expertise in PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.
  • Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).
  • Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE and HSPICE.
  • Must be based in or eligible to work in the US at the Santa Clara, Phoenix, or Hillsboro sites.

Nice to have

  • Ph.D. in Electrical Engineering or a related field.
  • 10+ years of experience in high-speed SerDes (56G/112G/224G).
  • Knowledge of PCIe 6.0+, 800G/1.6T Ethernet, and JESD protocols.
  • Experience in behavioral modeling (Verilog-A), MATLAB analysis, and automation scripting (Python/Tcl/Perl).

Culture & Benefits

  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation programs.
  • Hybrid work model allowing a split between on-site and off-site work.
  • Collaborative and knowledge-sharing engineering culture.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →