Analog Layout Engineer (FinFET)

TL;DR

Analog Layout Engineer (FinFET): Development of high-speed analog and mixed-signal IPs for HBM, UCIe, and PLL using 3nm and 2nm FinFET technology with an accent on high-performance computing and AI markets. Focus on layout optimization for power and performance and ensuring first-time-right quality for complex circuits like DACs and ADCs.

Location: Onsite in Allentown, PA or Fort Collins, CO, USA

Salary: $108,000 - $172,800

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Perform layout and verification of PLLs, Phase Interpolators, and high-speed clock distribution networks.
• Develop detailed layouts for Rx Decision-Feedback Equalizers, deserializers, TX drivers, and serializers.
• Design and verify high-speed DACs and ADCs.
• Optimize circuit layouts for power, performance, and integration into higher-level IPs and SOCs.
• Collaborate with a multi-geographical team to develop state-of-the-art integrated circuits.

Requirements

• BS degree in Electrical Engineering with 8+ years of experience, or MS degree with 6+ years of experience.
• Extensive experience in layout of high-speed custom analog and digital circuits (Serdes, HBM, UCIe, PLL).
• Proficiency with the Cadence Virtuoso tool suite for schematic capture and layout.
• Proven experience in advanced FinFET nodes.
• Deep understanding of layout fundamentals and the ability to solve complex circuit layout problems.

Culture & Benefits

• Comprehensive benefits package including medical, dental, and vision plans.
• 401(K) participation with company matching and Employee Stock Purchase Program (ESPP).
• Financial incentives including a discretionary annual bonus and competitive equity grants.
• Paid sick leave, vacation time, and company-paid holidays.
• Employee Assistance Program (EAP) for holistic support.