Senior Photolithography Process Engineer (Semiconductors)

TL;DR

Senior Photolithography Process Engineer (Semiconductors): Managing and optimizing photolithography processes in a high-volume wafer manufacturing environment with an accent on cost reduction, process stability, and tool utilization. Focus on implementing SPC using Six-Sigma methodology, developing standard work procedures, and leading cross-functional teams to ensure zero-defect manufacturing.

Location: Onsite in Chandler, USA

Company

A world leader in secure connectivity solutions for embedded applications serving automotive, industrial, IoT, and mobile markets.

What you will do

• Reduce costs associated with wafer scrap and photo rework to improve overall yield.
• Develop and document standard work procedures for Out of Control Action Plans.
• Implement process SPC and optimization using Six-Sigma statistical methodology.
• Improve tool utilization and availability while collaborating on capacity planning and modeling.
• Lead cross-functional and lean activity teams to enhance process integration and reduce variation.
• Train process technicians and FAB associates on tool operation and wafer disposition.

Requirements

• BS or MS degree in engineering or a relevant field of studies.
• More than 5 years of process engineering experience in a high-volume semiconductor manufacturing environment.
• Strong proficiency in Six-Sigma statistical methodology.
• Experience with ASML Scanner, Canon Stepper, TEL ACT 8/Mark 7 track, or KLA 8100 CDSEM is highly desirable.

Culture & Benefits

• Comprehensive online and offline learning opportunities for professional skill development.
• Inclusive work environment with a strong commitment to diversity, equality, and sustainability.
• Structured career development opportunities within a global semiconductor leader.