Design Engineering Architect (Semiconductor)

TL;DR

Design Engineering Architect (RTL/Semiconductor): Leading front-end design projects for IPs and subsystems with an accent on microarchitecture development and PPA goal achievement. Focus on writing and optimizing RTL code, overseeing pre-silicon verification, and collaborating with cross-functional teams to ensure successful SoC delivery.

Location: Austin, USA

Company

A global leader in electronic design automation (EDA) software and semiconductor hardware design tools.

What you will do

• Guide and mentor a team of RTL design engineers to foster a collaborative and innovative environment.
• Define and develop microarchitectural features for IPs and subsystems to ensure PPA goals are met.
• Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL for complex digital logic.
• Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), and Formal Verification (FV).
• Collaborate with Design Verification, Physical Design, Architecture, and firmware engineers for successful project delivery.

Requirements

• 10+ years of experience in Front End design and/or verification.
• BS/MS degree in Engineering or Computer Sciences.
• Proven experience in leading and managing complex engineering projects.
• Expertise in RTL design (Verilog) and simulator debuggers.
• Hands-on experience in Synthesis, SDC creation, and supporting PD and STA teams.
• Experience driving results within a multi-disciplinary organization.

Nice to have

• Experience with the hirify.global front-end toolset.
• Strong communication and design management skills.