Senior Engineer II - Physical Design (Semiconductor)

Location: Chandler, Arizona, United States

Company

hirify.global develops semiconductor products, including microcontrollers and microcontroller-based system-on-chip solutions.

What you will do

• Implement complex hierarchical, low-power mixed-signal microcontroller and SoC designs using FLASH process technologies.
• Execute physical design projects from design exploration through GDSII delivery and metal-only ECO implementation.
• Perform floorplanning, power-domain planning, placement, optimization, clock tree synthesis, routing, and timing closure.
• Conduct timing, signal integrity, power integrity, IR drop, electromigration, DRC, and LVS analysis for chip- and block-level designs.
• Develop and document physical design flows and methodologies, including support for test chip shuttles.
• Collaborate with synthesis, DFT, IP, CAD, and external vendor teams to resolve technical issues and achieve timely tapeout.

Requirements

• Bachelor's or master's degree in Electrical or Electronic Engineering, or equivalent.
• At least 5 years of hands-on physical design experience with a strong record of successful project execution.
• Advanced knowledge of place-and-route methodologies and low-power physical design flows.
• Experience with physical implementation and analysis tools such as Innovus, Fusion Compiler, Calibre, RedHawk, or StarRCxt.
• Strong scripting skills in TCL, Perl, and Shell, with working knowledge of Verilog and VHDL.
• Strong analytical, debugging, communication, and independent problem-solving abilities.

Nice to have

• Familiarity with advanced process nodes.

Culture & Benefits

• Full-time employment within a large global semiconductor organization.
• Employee development and career growth programs.
• Work involves approximately 90% sitting and may include working independently and around others.
• Travel requirement: 0%–25%.