Senior Verification Engineer (Automotive)

TL;DR

Senior Verification Engineer (SystemVerilog/UVM): Developing and executing verification plans for automotive MCU/MPU digital IPs with an accent on UVM testbenches, functional coverage, and formal verification. Focus on ensuring zero-defect digital IPs, optimizing engineering efficiency through AI/LLM approaches, and mentoring junior engineers.

Location: Austin, TX (Office)

Company

hirify.global develops best-in-class digital IPs for automotive and advanced microcontroller businesses, enabling secure and autonomous vehicles.

What you will do

• Define and execute comprehensive verification plans for digital IPs.
• Develop and implement verification testbenches using UVM, including drivers, monitors, and scoreboards.
• Create directed and constrained-random stimulus and maintain SystemVerilog assertions (SVA).
• Analyze RTL, functional coverage, and assertion coverage results to ensure quality.
• Apply formal verification methodologies to achieve a zero-defect mindset.
• Provide technical leadership and mentor a small team of engineers.

Requirements

• BSEE with 5+ years, MSEE with 3+ years, or PhD with 1+ year of semiconductor industry experience.
• Strong expertise in Verilog, SystemVerilog, and class-based verification (OVM/UVM).
• Knowledge of protocols such as DDR, PCIe, and AMBA (CHI, ACE, AXI).
• Proficiency in scripting with Python, Perl, and UNIX/Linux.
• Experience with low-power verification using CPF/UPF.
• Must be based in or able to work from the Austin, TX office.

Nice to have

• Experience with FPGA, emulation, or prototyping platforms (e.g., HAPS, Palladium, Zebu).
• Knowledge of VHDL.
• Understanding of power management concepts.
• Experience leveraging AI/LLM-based approaches for engineering efficiency.

Culture & Benefits

• Collaborative environment partnering with global SoC and IP teams.
• Commitment to equal opportunity and affirmative action.
• Support for disabled individuals through reasonable accommodations.