DFT Engineer (Semiconductors)

TL;DR

DFT Engineer (Semiconductors): Designing and implementing chip-level Design For Test architectures with an accent on scan, BIST, and ATE debugging. Focus on verifying DFT logic through simulation, performing static timing analysis, and ensuring successful chip bring-up.

Location: Onsite in Shanghai, China

Company

Global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Participate in chip level DFT architecture definition.
• Implement basic DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
• Verify all DFT logics and test patterns using simulation.
• Perform static timing analysis for various test modes.
• Participate in ATE bring-up and debug DFT patterns on ATE.

Requirements

• Proven experience in DFT architecture and implementation.
• Hands-on expertise with scan, boundary scan, Mem BIST, and Logic BIST.
• Experience with simulation-based verification of test patterns.
• Knowledge of static timing analysis (STA).
• Ability to debug and bring up patterns on ATE.
• Must be based in or able to work onsite in Shanghai, China.