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12 часов назад

Experienced DFT ATPG Engineer

105 650 - 200 340$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Мэтч & Сопровод

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Описание вакансии

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TL;DR

Experienced DFT ATPG Engineer: Develops logic design, RTL coding, simulation, DFT timing closure support, and test content generation for DFx content including SCAN, MBIST, and BSCAN with an accent on architecture and microarchitecture definition, optimization for power, performance, area, timing, test coverage. Focus on integrating DFT into SoC, verification of features, post-silicon debug, and HVM content for ATE rapid bring-up.

Location: US, Massachusetts (Beaver Brook) primary or US, California (Santa Clara); hybrid work model splitting time between on-site and off-site.

Salary: $105,650–$200,340

Company

Semiconductor leader in Data Center Group delivering Xeon-based and custom x86 solutions for compute, web services, HPC, and AI-accelerated systems.

What you will do

  • Develop logic design, RTL coding, simulation, and DFT timing closure for blocks, subsystems, and SoC.
  • Define architecture and microarchitecture features for DFT including TAP, SCAN, MBIST, BSCAN, and in-system test.
  • Generate and optimize test content for manufacturing, achieving power, performance, area, timing, coverage, and DPM goals.
  • Integrate DFT blocks into functional IP and SoC, supporting customers for high-quality integration.
  • Drive verification of DFT design, resolve RTL test failures, and collaborate on post-silicon validation and debug.
  • Develop HVM content for ATE bring-up and production ramp, ensuring high test coverage and quality objectives.

Requirements

  • BS EE/CE or related STEM + 3+ years DFT experience OR MS EE/CE + 1+ years DFT experience
  • 1+ years with tools like Siemens Tessent, Spyglass, Fusion Compiler, VCS
  • 1+ years scan insertion, low coverage debug, GLS debug, post-silicon debug

Nice to have

  • Experience with ATE and test content for high-volume manufacturing.
  • Effective collaboration and communication skills.
  • Strong problem-solving for complex design challenges.
  • Drive innovation in DFT methodologies.

Culture & Benefits

  • Competitive pay, stock bonuses, health, retirement, and vacation benefits.
  • Hybrid work model eligible.
  • Shift 1 (United States of America).

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