RTL Design Engineer

TL;DR

RTL Design Engineer (ASIC): Developing specifications, micro-architecture, and RTL design of mission-critical blocks for next-generation mixed-signal ASICs with an accent on state machines, FIFOs, high-speed data paths, and IP integration. Focus on collaborating with verification and physical design teams, providing timing constraints, STA support, and post-silicon debug for first-pass success.

Location: North Reading, MA, US

Salary: $123,100 - $196,900

Company

Global test and automation specialists powering next-generation semiconductor technologies through advanced ASIC solutions.

What you will do

• Develop specifications, micro-architecture, and RTL for mission-critical blocks in collaboration with chip architects.
• Integrate industry-standard and custom IPs into large mixed-signal ASICs.
• Collaborate with verification team on test plans, debug, and coverage closure.
• Provide timing constraints and STA support to physical design for timing closure.
• Support post-silicon lab bringup and debug.

Requirements

• BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
• Extensive RTL design experience in Verilog.
• Design of state machines, FIFOs, high-speed data paths, arbitration logic, and DFT.
• Experience with logic synthesis, timing constraints, CDC, and STA.
• Experience with high-speed memory and serial interfaces.
• Automation scripting with Python, Tcl, or Make.

Culture & Benefits

• Comprehensive health benefits including medical, dental, vision, FSA, life, and disability insurance.
• Retirement savings plans, paid vacation, holidays, and tuition assistance.
• Inclusive work environment fostering innovation, diversity, and high performance.
• Discretionary bonuses based on financial performance.