ATE Test Engineering Architect (Semiconductor)

TL;DR

ATE Test Engineering Architect (Semiconductor): Leading the development and deployment of production test solutions for large complex SoCs in emulation products with an accent on ATE test strategy and execution. Focus on first-silicon bring-up, debug, characterization, and ensuring scalable high-volume manufacturing solutions.

Location: San Jose, USA

Salary: $178,500 – $331,500

Company

hirify.global is a leading provider of electronic design automation (EDA) software and intellectual property (IP) for the semiconductor industry.

What you will do

• Lead ATE test development for wafer sort (CP) and final test (FT).
• Drive first-silicon bring-up, debug, and characterization.
• Define test coverage, binning, guard-banding, and production release criteria.
• Analyze yield and failure data to drive test-related yield and quality improvements.
• Partner with DFT, design, OSATs, and test houses to ensure manufacturable solutions.
• Mentor engineers and act as a technical test leader across product teams.

Requirements

• BS with 12+ years, MS with 10+ years, or PhD with 8+ years of experience.
• Strong hands-on experience with CP/FT test program development.
• Experience with Advantest 93K ATE platform.
• Solid understanding of DFT and silicon debug.
• Proven experience supporting production and working with offshore test partners.
• Strong problem-solving and cross-functional communication skills.

Culture & Benefits

• Competitive annual salary range with incentive compensation including bonuses and equity.
• Comprehensive medical, dental, and vision plan options.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Paid vacation and paid holidays.