RTL2GDS, Product Engineering Architect

Location: San Jose, California, United States

Annual salary: $178,500–$331,500, plus potential bonus, equity, and benefits.

Company

hirify.global develops advanced chip design software tools through its Digital and Signoff Group.

What you will do

• Support hirify.global digital products as a technical resource for customers and internal development teams.
• Provide place-and-route expertise across the RTL-to-GDSII design flow.
• Track and resolve customer issues in collaboration with R&D and release teams.
• Conduct design benchmarks and diagnose implementation challenges.
• Develop innovative flows and methodologies tailored to customer requirements.

Requirements

• BS in Electrical Engineering and at least seven years of experience in digital implementation as a design or product engineer.
• Strong understanding of ASIC design methodologies and VLSI physical design.
• Hands-on experience with timing closure and PPA optimization at 7nm and below.
• Knowledge of timing analysis, clock tree synthesis, routing optimization, and silicon signoff challenges.
• Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below.
• Strong verbal and written communication skills.

Nice to have

• Proficiency in scripting languages or AI tools for productivity enhancement.

Culture & Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential incentive compensation including bonus and equity.